1. Field of the Invention
This invention relates to voltage controlled oscillators and to integrated circuits containing voltage controlled oscillators.
2. Description of Related Art
A voltage controlled oscillator (VCO) provides an oscillating signal with frequency that depends on a control voltage. VCOs are commonly employed in phase-locked loops (PLL) such as shown in FIG. 1. In FIG. 1, a VCO 140 receives a control voltage VCNTRL from a charge pump 130 and provides an oscillating signal CLK. Signal CLK passes through a variable divider or programmable counter 150 which produces a second oscillating signal CLK2. A phase comparator 120 compares signal CLK2 to a reference signal REF generated by a reference oscillator 110 and generates control signals UP and DOWN for charge pump 130. Charge pump 130 increases, decreases, or maintains voltage VCNTRL as necessary to keep signals REF and CLK2 in phase.
FIG. 2 shows a differential mode VCO 200. VCO 200 includes an odd number of delay cells 212, 214, and 216 connected in a ring. Each delay cell inverts a pair of signals A and B as they propagate around the ring. When VCO 200 is operating properly, signals A and B are complementary, and a clock signal CLK is derived from the voltage difference between complementary oscillating signals A and B. Delay cells 212, 214, and 216 are tied to control voltage VCNTRL which controls the delay of each cell and the frequency of VCO 200. An advantage of differential mode VCO 200 is clock signal CLK being derived from a voltage difference is less affected by noise in the supply voltage.
A problem with VCO 200 is that the delay for signal A through delay cells 212, 214, and 216 can differ from the delay for signal B. In the worst case, the difference in delays causes signals A and B to become in phase, and signal CLK does not oscillate. Another problem is that VCO 200 has low differential gain at high frequencies. The speeds of delay cells 212, 214, and 216 are typically limited by gate delay for charging of transistor gates. Gate delay is a function of (C/I)dV where C is the capacitance of a transistor, I is the current charging the gate, and dV is the change in gate voltage. Lower capacitance and higher current increase speed, but also reduce the swing in output voltage and the difference between signals A and B. At high frequencies (above about 300 MHz), the output voltage may become too low to switch a standard CMOS transistor.